SMSC DS LPC47N252

Rev. 09/06/2000

LPC47N252

PRELIMI NARY

Advanced Notebook I/O Controller

with On-Board FLASH

FEATURES

3.3V Operation with 5V Tolerant Buffers

ACPI 1.0b , PC99/PC2001 Compliant

LPC Interface with Clock Run Support

Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems

15 Direct IRQs

Four 8-Bit DMA Channels

ACPI SCI Interface

nSMI

Shadowed write only registers

Internal 64K Flash ROM

Programmed From Direct Parallel Interface,
8051, or LPC Host

2k-Byte Lockable Boot Block

Can be Programed Without 8051
Intervention

Three Power Planes

Low Standby Current in Sleep Mode

Intelligent Auto Power Management for
Super I/O

ACPI Embedded Controller Interface

Configuration Register Set Compatible with ISA
Plug-and-Play Standard (Version 1.0a)

High-Performance Embedded 8051 Keyboard
and System Controller

Provides System Power Management

System Watch Dog Timer (WDT)

8042 Style Host Interface

Supports Interrupt and Polling Access

256 Bytes Data RAM

On-Chip Memory-Mapped Control Registers

Access to RTC and CMOS Registers

Up to 16x8 Keyboard Scan Matrix

Two 16 Bit Timer/Counters

Integrated Full-Duplex Serial Port Interface

Eleven 8051 Interrupt Sources

Thirty-Two 8-Bit, Host/8051 Mailbox
Registers

Thirty-six Maskable Hardware Wake-Up
Events

Fast GATEA20

Fast CPU_RESET

Multiple Clock Sources and Operating
Frequencies

IDLE and SLEEP Modes

Fail-Safe Ring Oscillator

Advanced Infrared Communications Controller
(IrCC 2.0)

IrDA V1.2 (4Mbps), HPSIR, ASKIR,
Consumer IR Support

Two IR Ports

Relocatable Base I/O Address

Real-Time Clock

MC146818 and DS1287 Compatible

256 Bytes of Battery Backed CMOS in Two
128-Byte Banks

128 Bytes of CMOS RAM Lockable in 4x32
Byte Blocks

12 and 24 Hour Time Format

Binary and BCD Format

A Standby Current (typ)

Two 8584-Style ACCESS.Bus Controllers

8051 Controlled Logic Allows ACCESS.Bus
Master or Slave Operation

ACCESS.Bus Controllers are Fully
Operational on Standby Power

2 Sets of Dedicated Pins per
ACCESS.BusController

Four independent Hardware Driven PS/2 Ports

83 General Purpose I/O Pins

36 Maskable Hardware Wake-Event
Capable

18 Programmable Open-Drain/Push-Pull
Outputs

16 Mapped into 8051 SFR Space

24 LPC/8051-Addressable

Three Programmable Pulse-Width Modulator
Outputs

Independent Clock Rates

6 Bit Duty Cycle Granularity

Note: Please see Addendum to LPC47N252 Data Sheet at http://www.smsc.com/main/datasheets/47n252add.pdf

SMSC DS - LPC47N252

Page 2

Rev. 09/06/2000

VCC1 and VCC2 operation mode

Dual Fan Tachometer Inputs

2.88MB Super I/O Floppy Disk Controller

Relocatable to 480 Different Base I/O
Addresses

15 IRQ Options

4 DMA Options

Open-Drain/Push-Pull Configurable Output
Drivers

Licensed CMOS 765B Floppy Disk
Controller

Advanced Digital Data Separator

Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core

Low Power CMOS Design with Sophisticated
Power Control Circuitry (PCC) Including
Multiple Powerdown Modes for Reduced
Power Consumption

Supports Two Floppy Drives on the FDD

Interface and Two Floppy Drives on the
Parallel Port Interface

12 mA FDD Interface Cable Drivers with

Schmitt Trigger Inputs

Licensed CMOS 765B Floppy Disk Controller
Core

Supports Vertical Recording Format

16-Byte

Data

FIFO

100% IBM Compatibility

Detects All Overrun and Underrun
Conditions

12 mA Drivers and Schmitt Trigger Inputs

DMA Enable Logic

Data Rate and Drive Control Registers

Enhanced Digital Data Separator

Low Cost Implementation

No Filter Components Required

2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250

Kbps Data Rates

Programmable Precompensation Modes

Multi-Mode Parallel Port with ChiProtect

Standard Mode IBM PC/XT, PC/AT, and

PS/2 Compatible Bi-directional Parallel Port

Enhanced Parallel Port EPP 1.7 and EPP
1.9 Compatible (IEEE 1284 Compliant)

IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)

ChiProtect Circuitry to Prevent Printer

Power-On Damage

Relocatable to 480 Different Base I/O
Addresses

15 IRQ Options

4 DMA Options

Microsoft and HP compatible High Speed

Mode

Floppy Disk Interface on Parallel Port

8051-Controlled Parallel Port Mode

Serial

Port

High-Speed NS16550A-Compatible UART
with 16-Byte Send/Receive FIFOs

Programmable Baud Rate Generator

Modem Control Circuitry Including 230k and

460k Baud

Relocatable to 480 Different Base I/O
Addresses

15 IRQ Options

ORDERING INFORMATION

Order Numbers:

LPC47N252-SG for 208 Pin FBGA Package

LPC47N252-SD for 208 Pin TQFP Package

SMSC DS LPC47N252

Page 3

Rev. 09/06/2000

GENERAL DESCRIPTION

The LPC47N252 is a 208-pin 3.3V LPC-based ACPI 1.0 and PC99/PC2001 compliant Notebook I/O Controller with
Fast Infrared for mobile applications. See FIGURE 2 LPC47N252 BLOCK DIAGRAM.

The LPC47N252 incorporates a high-performance 8051-based keyboard controller; a 64k byte internal Flash ROM,
four PS/2 ports; a real-time clock; SMSC's true CMOS 765B floppy disk controller with advanced digital data
separator and 16-byte data FIFO; an NS16C550A-compatible UART, SMSC's advanced Infrared Communications
Controller (IrCC 2.0) with a UART and a Synchronous Communications Engine to provide IrDA v1.1 (Fast IR)
capabilities; one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support; two 8584-style Access
Bus controllers with two Sets of Dedicated Pins per ACCESS.Bus Controller; a Serial IRQ peripheral agent interface;
an ACPI Embedded Controller Interface; General Purpose I/O pins including eight pass through ports; three
independently programmable pulse width modulators; two-floppy direct drive support; and maskable hardware wake-
up events.

The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to
providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's
patented data separator technology, allowing for ease of testing and use. The parallel port is compatible with IBM
PC/AT architecture, as well as EPP and ECP. The 8051 controller can also take control of the parallel port interface
to provide remote diagnostics or "Flashing" of the Flash memory.

The LPC47N252 has three separate power planes to provide "instant on" and system power management functions.
Additionally, the LPC47N252 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple
low power down modes. Wake-up events and ACPI-related functions are supported through the SCI Interface.

The LPC47N252's configuration register set is compatible with the ISA Plug-and-Play Standard (Version 1.0a) and
provides the functionality to support Windows '95.The legacy host Super I/O Configuration and Alternate Super I/O
Configuration decode ranges comply with the Low Pin Count Interface Specification, Revision 1.0.

Through internal configuration registers, each of the LPC47N252's logical device's I/O address, DMA channel and
IRQ channel may be programmed. There are 480 I/O address location options, 15 IRQ options, and four DMA
channel options for each logical device.

The LPC47N252 does not require any external filter components and is, therefore, easy to use and offers lower
system cost and reduced board area. The LPC47N252 is software and register compatible with SMSC's proprietary
82077AA core.

80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123

Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC, Ultra I/O, ChiProtect, and Multi-Mode are
trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit
diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is
assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact
your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to
the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on
your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of
your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's
functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended,
authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe
property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the
risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's
website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL
WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR
NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.

SMSC DS LPC47N252

Page 4

Rev. 09/06/2000

TABLE OF CONTENTS

FEATURES

.................................................................................................................................................................. 1

GENERAL DESCRIPTION

........................................................................................................................................ 3

1.1

EFERENCE

OCUMENTS

................................................................................................................................. 12

1.1.1

Intel Low Pin Count Specification ......................................................................................................... 12

1.1.2

PCI Local Bus Specification.................................................................................................................. 12

1.1.3

Advanced Configuration and Power Interface Specification................................................................. 12

1.1.4

LPC47N252 Notebook I/O Controller with Enhanced Keyboard Control and System Management.... 12

1.1.5

IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard ...................................... 12

TQFP PIN CONFIGURATION.............................................................................................................................. 13

PIN FUNCTIONS.................................................................................................................................................. 15

3.1

ESCRIPTION

UNCTIONS

..................................................................................................................... 16

3.1.1

Alternate Function

Pins

........................................................................................................................ 22

3.2

OWER

ONFIGURATION

.................................................................................................................................. 23

FUNCTIONAL DESCRIPTION............................................................................................................................. 25

4.1

OST

ROCESSOR

NTERFACE

(LPC) ............................................................................................................... 26

4.1.1

LPC Bus Cycles Description................................................................................................................ 26

4.1.2

LPC Bus Cycles Summary ................................................................................................................... 27

4.1.3

Standard LFRAME# Usage .................................................................................................................. 27

4.1.4

Abort Mechanism.................................................................................................................................. 28

4.1.5

I/O Read And Write Cycles................................................................................................................... 28

4.1.6

Dma Read And Write Cycles................................................................................................................ 28

4.1.7

DMA Request ....................................................................................................................................... 28

4.1.8

SYNC Protocol...................................................................................................................................... 30

4.1.9

I/O And DMA Start Fields ..................................................................................................................... 31

4.1.10

Reset Policy.......................................................................................................................................... 31

4.1.11

Electrical Specifications........................................................................................................................ 31

4.1.12

Wait State Requirements...................................................................................................................... 31

4.1.13

LPC Transfer Sequence Examples ...................................................................................................... 31

4.1.14

LPC Power Management...................................................................................................................... 36

FLOPPY DISK CONTROLLER............................................................................................................................ 38

FDC I

NTERNAL

EGISTERS

.......................................................................................................................................... 38

Status Register A (SRA)....................................................................................................................................... 38
Status Register B (SRB)....................................................................................................................................... 39

Digital Output Register (DOR) .............................................................................................................................. 41
Tape Drive Register (TDR)................................................................................................................................... 42

Data Rate Select Register (DSR) ......................................................................................................................... 43

Main Status Register ............................................................................................................................................ 45
Data Register (FIFO) ............................................................................................................................................ 46

Digital Input Register (DIR)................................................................................................................................... 46
Configuration Control Register (CCR) .................................................................................................................. 48

STATUS REGISTER ENCODING............................................................................................................................ 48
5.1

FDC RESET ................................................................................................................................................. 50

5.2

FDC MODES OF OPERATION.................................................................................................................... 51

5.2.1

PC/AT mode ......................................................................................................................................... 51

5.2.2

PS/2 mode............................................................................................................................................ 51

5.2.3

Model 30 mode..................................................................................................................................... 51

5.3

DMA TRANSFERS....................................................................................................................................... 51

5.4

CONTROLLER PHASES.............................................................................................................................. 51

5.4.1

Command Phase.................................................................................................................................. 51

5.4.2

Execution Phase................................................................................................................................... 51

5.4.3

Result Phase ........................................................................................................................................ 52

5.5

COMMAND SET/DESCRIPTIONS............................................................................................................... 53

5.6

FDC INSTRUCTION SET............................................................................................................................. 55

5.7

FDC DATA TRANSFER COMMANDS ......................................................................................................... 61

SMSC DS LPC47N252

Page 5

Rev. 09/06/2000

5.7.1

Read Data............................................................................................................................................. 61

5.7.2

Read Deleted Data ............................................................................................................................... 62

5.7.3

Read A Track........................................................................................................................................ 63

5.7.4

Write Data............................................................................................................................................. 64

5.7.5

Write Deleted Data ............................................................................................................................... 64

5.7.6

Verify..................................................................................................................................................... 64

5.7.7

Format A Track..................................................................................................................................... 65

5.8

FDC CONTROL COMMANDS ..................................................................................................................... 67

5.8.1

Read ID................................................................................................................................................. 67

5.8.2

Recalibrate............................................................................................................................................ 67

5.8.3

Seek...................................................................................................................................................... 67

5.8.4

Sense Interrupt Status.......................................................................................................................... 68

5.8.5

Sense Drive Status............................................................................................................................... 68

5.8.6

Specify.................................................................................................................................................. 68

5.8.7

Configure .............................................................................................................................................. 69

5.8.8

Version.................................................................................................................................................. 69

5.8.9

Relative Seek........................................................................................................................................ 70

5.8.10

Perpendicular Mode.............................................................................................................................. 70

5.8.11

Lock ...................................................................................................................................................... 71

5.8.12

Enhanced DUMPREG .......................................................................................................................... 72

5.9

COMPATIBILITY .......................................................................................................................................... 72

5.9.1

Parallel Port FDC.................................................................................................................................. 72

5.9.2

Hot Swappable FDD Capability ............................................................................................................ 72

5.10

FDC FORCE WRITE PROTECT .................................................................................................................. 73

ACPI EMBEDDED CONTROLLER...................................................................................................................... 75

6.1

ECI C

ONFIGURATION

EGISTERS

..................................................................................................................... 75

6.2

ECI R

UNTIME

EGISTERS

................................................................................................................................ 76

6.3

EC_STATUS R

EGISTER

................................................................................................................................. 76

6.4

EC_COMMAND R

EGISTER

............................................................................................................................ 77

6.5

EC_DATA R

EGISTER

..................................................................................................................................... 78

SERIAL PORT (UART) ........................................................................................................................................ 79

7.1

REGISTER DESCRIPTION.......................................................................................................................... 79

7.1.1

Receive Buffer Register (RB) ............................................................................................................... 79

7.1.2

Transmit Buffer Register (TB)............................................................................................................... 79

7.1.3

Interrupt Enable Register (IER) ............................................................................................................ 79

7.1.4

Fifo Control Register (FCR).................................................................................................................. 80

7.1.5

Interrupt Identification Register (IIR)..................................................................................................... 81

7.1.6

Line Control Register (LCR) ................................................................................................................. 82

7.1.7

Modem Control Register (MCR) ........................................................................................................... 83

7.1.8

Line Status Register (LSR)................................................................................................................... 84

7.1.9

Modem Status Register (MSR)............................................................................................................. 85

7.1.10

Scratchpad Register (SCR) .................................................................................................................. 86

7.1.11

Programmable Baud Rate Generator (And Divisor Latches DLH, DLL)............................................... 86

7.2

FIFO INTERRUPT MODE OPERATION...................................................................................................... 87

7.3

FIFO POLLED MODE OPERATION ............................................................................................................ 88

7.3.1

Effect Of The Reset on Register File.................................................................................................... 89

7.3.2

NOTES ON SERIAL PORT FIFO MODE OPERATION....................................................................... 90

7.3.3

TX AND RX FIFO OPERATION ........................................................................................................... 90

INFRARED COMMUNICATIONS CONTROLLER (IRCC 2.0) ............................................................................ 92

8.1

IRRX/IRTX PIN ENABLE.............................................................................................................................. 93

8.2

IR REGISTERS - LOGICAL DEVICE 5 ........................................................................................................ 93

8.3

IR DMA C

HANNELS

........................................................................................................................................ 93

8.4

IR IRQ

......................................................................................................................................................... 94

8.4.1

Software Select Registers A and B....................................................................................................... 94

8.5

IR H

ALF

UPLEX

IMEOUT

............................................................................................................................... 94

8.6

IRTX O

UTPUT

INS

EFAULT

........................................................................................................................... 94

PARALLEL PORT................................................................................................................................................ 95

9.1

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .............................................................. 96

9.1.1

Register Definition ................................................................................................................................ 96

9.2

EXTENDED CAPABILITIES PARALLEL PORT......................................................................................... 102

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